In Smart Power IC technology, low voltage and high voltage transistors are integrated on the same substrate. The junction isolation is obtained with reverse biased of PN junctions. During commutation of high-voltage transistors, parasitic currents, consisting of electrons and holes are coupled by the sensitive part of the IC. This electrical coupling noise can severely disturb low voltage analog circuits located in the surroundings and may also deeply affect the functionality of the chip.
Such parasitic signals represent the major cause of failure and induce expensive circuit redesign in power integrated circuits. The CAD simulation of these coupling effects, where minority and majority carriers need to be accounted for is done using a new junction equivalent model.